1. Field of the Invention
The present invention relates to a node device of an ATM (Asynchronous Transfer Mode) communication network and a method of a failure alarm notification.
This invention is based on Patent Application No. Hei 10-172106 filed in Japan, the content of which is incorporated herein by reference.
2. Background Art
Specifications for an OAM (Operation, Administration, and Maintenance) processing is generally used in an ATM communication network for an ATM level failure alarm notification, and the processing steps are provided in ITU-T Rec.I610 xe2x80x9cB-ISDN Operation and Maintenance Principals and Functionxe2x80x9d.
FIG. 1 is a schematic diagram showing a relationship between the lines of the ATM communication network and the connections. In the figure, the reference numeral 101 indicates a SDH (Synchronous Digital Hierarchy) line, 102 and 103 indicate VP1 (first virtual path) and VP2 (second virtual path), respectively, which are both multiplexed with the SDH 101, and 104 and 105 indicate connections VC1 (first Virtual connection) and VC2 (second Virtual Connection), respectively, which are multiplexed with VP1 and VP2, respectively.
When a failure occurs in the SDH line 101, a VP-AIS (Alarm Indication Signal) is sent downstream to respective VPs which are multiplexed with the SDH 101. At the end point of the VPC (Virtual Path Connection), the VC-AIS is sent downstream to each VC (Virtual Connection), which is multiplexed with each VP.
Referring to FIG. 1, when a failure occurs in the SDH line 101, the VP-AIS is sent to VP1102 and VP2103, respectively, which are multiplexed with SDH 101.
At the end point of the VPC, the VC-AIS is sent to VC1104 and VC2105, respectively, which are multiplexed with VP1102 and VP2103.
At the end point of VPC, the VP-AIS is terminated, and the VP-RDI (Remote Defect Indication) is sent to the end point of the opposite VP.
Similarly, the VC-AIS is terminated at the end point of VCC, and the VC-RDI is sent to the end point of the opposing VC.
FIG. 2 is a block diagram showing VCs (Virtual Connection) from the sending side VC user to the receiving side VC user. The reference numeral 202 indicates the sending side VC user, VCX1; 203 indicates a sending side node, VPX1; 204 indicates a relay node, VPX2; 205 indicates a receiving side node, VPX 3; and 206 indicates a receiving side VC user, VCX2. A virtual connection VCC 216 connects from the sending side VC user, VCX1202, to the receiving side VC user VCX2206, and the virtual connection 216 is multiplexed with the virtual path VPC215 in between the sending side node VPX1203 and the receiving side node VPX3205.
Hereinafter, a case will be described when a failure 201 occurs at a position in a VP indicated by a mark X, which is located between the node VPX1203 and the node VPX2204, as shown in FIG. 2.
When the failure is detected at the relay node VPX2204 located downstream from the position of the failure, the relay node VPX2204 sends a signal VP-AIS 207 down stream from the node. Since the receiving side node VPX3205 that has received VP-AIS 207 is the end point of the VPC 215 in which the failure occured, the VP-AIS 207 is terminated at the node 205 and VP-RDI 210 is sent upstream to the opposite VP which forms a pair with the VP in which the failure occured. The receiving side node VPX3205 sends VC-AIS 208 down stream to the VC which is multiplexed with the failed VP for notifying the failure alarm.
The receiving side VC user VCX2206, which is multiplexed with the failed VP and which is the end point of the VC, terminates the received VC-AIS 208, and sends VC-RDI 209 upstream from the device to another VC which forms a pair of the VC which received the failure signal. The VPX3205, VPX2204, and VPX1203 send VC-RDI 209 as it is supplied from the VCX2206 to the VCX1202 upstream.
Since VPX1203 is the end point of the VPC 215, the VPX1203 terminates the VP-RDI 212 sent from the VPX3205. By receiving and terminating the VP-RDI 212, the VPX1203 can recognize the position of the failure marked by X.
Since VCX1202 is the end point of VCC 216, it receives and terminates VC-RDI 214 sent from the VCX2206.
In order to carry out the above described processing, respective nodes shown in FIG. 2 are constructed as shown in FIG. 3 or in FIG. 4.
FIG. 3 is a diagram showing structures of the relay nodes VPX2204 in FIG. 2, which is comprised of line processing interfaces (301-1, 301-2, . . . , 301-k, 301-N, only 301-1 and 301-n are shown in the figure), provided for respective lines (numbers of lines are 1, 2, . . . , k, . . . , N), an ATM switch 302, and a processor 303.
The line processing interfaces for respective lines are the same and a line processing interface 301-1 will be described. The line processing interface 301-1 is provided with a line receiving portion 311-1 which terminates the line, a failure notifying portion 312-1 for notifying that the failure in a line has been detected, a header converting portion 313-1 for converting a header of received data (cell), a header conversion table 314-1, which stores notifications for replacing the header, and which is referred to by the header converting portion, a cell inserting portion 315-1 for inserting a cell to communicate the failure notice, and a line sending portion 316-1.
When the line receiving portion 311-1 of the line processing interface 301-1 detects an LOS (Loss Of Signal), the failure notice portion 312-1 is informed about this detection, and the cell insertion portion 315-1 prepares for inserting the VP-AIS cell.
An address of the VP-AIS cell is determined by the header conversion portion 313-1, and the address is added to the header of the VP-AIS cell as VPIs (VP identifiers). The VP-AIS cell, to which the address is added, is input into the ATM switch 302 from the cell inserting portion 315-1.
FIG. 4 is a block diagram showing the structure of a node which is the end point of the VPC, such as the receiving side node VPX3205 shown in FIG. 2, and which is comprised of line processing interfaces 401-1, 402-1, . . . , 401-k, . . . , 401-N provided for respective lines 1, 2, . . . , k, . . . , N, an ATM switch 402, and a processor 403.
Since the line processing interfaces for respective lines have the same structure, the structure of the line processing interface is explained using the first line processing interface 401-1. The first line processing interface 401-1 comprises the line receiving portion 411-1 which terminates the line, a failure notifying portion 412-1 for notifying that a failure has been detected in a line, a header converting portion 413-1 which renews the header of the received data (cell), a header conversion table 414-1 which stores data for renewing data and which is referred by the header converting portion 413-1, an upstream cell inserting portion 415-1 for inserting a cell for communicating the failure notice, a cell inserting portion 416-1, and a line transmitting portion 417-1.
When the LOS is detected at the line receiving portion 411-1 of the line processing interface 401-1, the detected signal is communicated to the failure notifying portion 412-1, and the cell inserting portion 412-1 prepares for inserting the VC-AIS cell as the end-point of the VP in response to an instruction from the failure notifying portion 412-1.
The address of the VC-AIS cell is determined by the header converting portion 413-1 and the result is added to the header of the VC-AIS as the VPI/VCI (VP Identifier/VC Identifier).
The VC-AIS to which the address has been added is input to an ATM switch 402 from the cell inserting portion 415-1.
Since this node is the end point of the VP, a preparation for inserting the VP-RDI cell is performed by the cell inserting portion 417-1.
The VP-RDI, to which the address is added, is sent to a VP, which forms a pair with the other VP in the upper stream by the line sending portion 416-1.
As described above, in the conventional node device in an ATM communication network, in order to add address information VPI or the VPI/VCI to the AIS or RDI cell which is the failure alarm signal, similar to the case of adding the VPI or the VPI/VCI to the usual OAM cell, the header converting portion 313-1 or 413-1 determines and add address information with reference to the header conversion table 314-1 or 414-1.
However, the problems are encountered that it takes a considerable time to refer to the header conversion table by normal software and the load for the processor is great when carrying out the operation of the software.
That is, it may be assumed that the processor for referring to the header conversion table 314-1 or 414-1 is included in the header converting portion 313-1 or 413-1, or that the header conversion table 314-1 or 414-1 is referred to by software which is operated by the processor 303 or 403. However, in either case, the problems remain that the load for the processor is quite large, and the reference operation takes a long time.
The object of the present invention is to provide a node device which, when a failure occurs upstream of the ATM communication network, can send the failure alarm notification quickly downstream from the ATM communication network, and to provide a method of the failure alarm notification by use of the present node device.
Each line processing interface constituting a node in an ATM communication network is composed of a pair of interfaces for up and down paths. Thus, when a failure occurs in, for example, the down path, and when the VP-AIS cell is sent by said line processing interface downstream, it is possible to use the VPI which is extracted from the cell header in the up path input in said line processing interface. Extraction of the VPI can be carried out by simple hardware; thereby, the VPI can be obtained more rapidly than the determination with reference to the header conversion table, and the load to the processor can be reduced.
According to the present invention, a node device in the ATM (Asynchronous Transfer Mode) network comprises:
line processing interfaces provided for respective lines of said ATM network;
ATM switches to which VPs (Virtual Path) output from said line processing interfaces are connected and to which VPs input to said line processing interfaces are connected; and
a processor for controlling said ATM switches and all of said line processing interfaces; and
said line processing interface comprises:
a line receiving portion for receiving an ATM cell from upstream of line;
a failure notification portion for communicating the failure of said VP when the failure is detected at said line receiving portion by interruption of the upstream ATM cell;
a cell extracting/generating portion for making a copy of the ATM cell which is input from said ATM switch to said line processing interface according to an instruction from said failure notification portion, when the failure of said VP is detected, and for generating the failure alarm signal cell using the copied data of the header of the cell;
a cell inserting portion for transferring the failure alarm signal cell generated at the cell extracting/generating portion to said ATM switch; and
a line sending portion for sending the cell input from said ATM switch to said upstream cell extracting/generating portion from the line processing interface.
In the node device of the present invention, said cell extracting/generating portion comprises:
a determination portion for determining the instruction from said failure notification portion;
a timer which is started by the determination portion, when the determination portion determines that said failure of the VP is notified;
a cell copying portion, which is started by the determination portion, when the determination portion determines that said VP failure notification is communicated for making a copy of the cell input from said ATM switch to said line processing interface;
a VPI extracting portion for extracting a VPI (VP identifier) from said cell copied at said cell copying portion; and
an AIS (Alarm Indication Signal) generating portion for generating the AIS cell, having the VPI extracted at the VPI extracting portion written at the header, for transferring said AIS to said cell inserting portion.
In the node device of the present invention, said determination portion activates said timer from the time when said determination portion receives the failure notification from said failure notification portion until the time when said determination portion receives the failure restoration notification, and said AIS cell generating portion generates AIS cell in the timing determined by said timer while the timer is operating.
In the node device of the present invention, said cell extracting/generating portion comprises:
a determination portion for determining the instruction from said failure notification portion;
a timer which is activated by said determination portion, when the determining potion determines that the failure of said VP is communicated;
a cell copying portion, that is started by the determination portion, when the determination portion determines that the failure of said VP is communicated, for making a copy of the cell input from said ATM switch to said line processing interface;
a VPI/VCI extracting portion for extracting the VPI/VCI (VCI is a VC identifier) from the cell copied by the cell copying portion;
an AIS generating portion for generating an AIS cell, having the VPI/VCI extracted at the VPI/VCI extracting portion written at the header, for transferring said AIS to said cell inserting portion;
an RDI generating portion for generating an RDI (Remote Defect Indication) cell, having a VPI extracted at said VPI/VCI extracting portion written at the header; and
an RDI cell inserting portion for transferring said RDI cell to said line sending portion.
Furthermore, said determination portion activates said timer from the time when said determination portion receives the failure notification from said failure notification portion until the time when said determination portion receives the failure recovery notification, and said AIS cell generating portion and said RDI generating portion generate said AIS cell and RDI cell, respectively, in the timing determined by said timer while the timer is operating.
According to the present invention, a method of the failure alarm notification comprises the steps of:
detecting a failure originating upstream from said VP by the line receiving portion of the line processing interface; and
transmitting a AIS cell downstream from said VP after generating said AIS cell having a VPI, which is the same VPI transmitting on the VP forming a pair with the failed VP.
The method of communicating the failure alarm comprises the steps of:
detecting a failure that has occurred upstream from a VP by the line receiving portion of the line processing interface;
transmitting an AIS cell downstream to said VP concerned after generating said AIS cell having a VPI/VCI, which is the same VPI/VCI transmitted on the VP forming a pair with the failed VP;
transmitting an RDI cell downstream from said VP after generating said RDI cell having a VPI, which is the same VPI transmitting on the VP forming a pair with the failed VP.